A novel and precise time domain description of MOSFET low frequency noise due to random telegraph signals

Nowadays, random telegraph signals play an important role in integrated circuit performance variability, leading for instance to failures in memory circuits. This problem is related to the successive captures and emissions of electrons at the many traps stochastically distributed at the silicon-oxide (Si-SiO2) interface of MOS transistors. In this paper we propose a novel analytical and numerical approach to statistically describe the fluctuations of current due to random telegraph signal in time domain. Our results include two distinct situations: when the density of interface trap density is uniform in energy, and when it is an u-shape curve as prescribed in literature, here described as simple quadratic function. We establish formulas for relative error as function of the parameters related to capture and emission probabilities. For a complete analysis experimental u-shape curves are used and compared with the theoretical aproach

Analysis of total ionizing dose effects on 0.13 µm technology-temperature-compensated voltage references

ABSTRACT: The purpose of this work is to briefly discuss the effects of the total ionizing dose (TID) on MOS devices in order to estimate the results of future irradiation tests on temperature-compensated voltage references that are implemented on a mixed-signal chip fabricated using IBM 0.13 µm technology. The analysis will mainly focus on the effects of the parametric variations on different voltage references. Monte-Carlo analyses were performed in order to determine the effects of threshold voltage shifts in each transistor on the output voltage

An electric-based model for coupling traps effect on random telegraph noise

In this work, we present a novel understanding about the anomalous Random Telegraph Noise (aRTN), asserting the existence of coupling effect among multiple traps regarding current amplitude deviation. Based on the examination in the literature of anomalous current fluctuation, we propose a model able to describe the equivalent filament resistance changes due to this process. Notwithstanding, the results obtained with our model fits with experimental current over time observations presented on literature. Given that RTN is still a concern for different technologies, such as MOSFETs, FinFets and ReRAMs, the model can be applied to understanding the dynamics of filament distribution and the trapping de-trapping activity

Monte Carlo simulation of hole transport in SiGe alloys

This paper employs Ensemble Monte Carlo method to simulate transport of holes in SiGe alloys. A three-band model was employed to describe the valence band of these alloys. The nonparabolicity and the warping effect of the heavy-hole and light-hole bands were considered in their dispersion relation, while the split-off band was described as parabolic and spherical. We consider phonon and alloy disorder scattering in these calculations. The mobility of holes for a range of SiGe al-loys was calculated at 300K. The simulation mobility results agree with the experimental data, implying that the selected transport model for holes in SiGe alloys is adequate

3-D TCAD Monte Carlo device simulator : state-of-the-art FinFET simulation

This work presents a comprehensive description of an in-house 3D Monte Carlo device simulator for physical mod-eling of FinFETs. The simulator was developed to consider var-iability effects properly and to be able to study deeply scaled devices operating in the ballistic and quasi-ballistic regimes. The impact of random dopants and trapped charges in the die-lectric is considered by treating electron-electron and electron-ion interactions in real-space. Metal gate granularity is in-cluded through the gate work functionvariation. The capability to evaluate these effects in nanometer3D devices makes the pre-sented simulator unique, thus advancing the state-of-the-art. The phonon scattering mechanisms, used to model the transport of electrons in puresilicon material system, were validated by comparing simulated drift velocities withavailable experi-mental data. The proper behavior of the device simulator is dis-played in a series of studies of the electric potentialin the device, the electron density, the carrier's energy and velocity, and the Id-Vg and Id-Vd curves

SGC : um ambiente para a automação de procedimentos de caracterização e teste

Este trabalho trata de ambientes de software para a realização de teste e caracterização de dispositivos, componentes ou circuitos eletro-eletrônicos, de forma automatizada. Ênfase especial é dada à problemática relacionada ao teste e caracterização automatizados de dispositivos e circuitos integrados. O assunto é tratado sob dois pontos de vista distintos e complementares: i) Sob o ponto de vista do engenheiro de teste e caracterização, que realiza experimentos físicos, que são as medidas e aquisições de dados, processa, visualiza e analisa dados. ii) Sob o ponto de vista do projetista de ferramentas de software, que desenvolve programas de computador para automatizar as tarefas rotineiramente realizadas durante o teste e a caracterização. Após a analise do assunto em questão, um ambiente de software (Framework), chamado SGC, é proposto e implementado. O SGC foi implementado em ambiente MS-WindowsTM através de um paradigma de orientação a objetos, e pretende atender as necessidades inerentes ao teste e caracterização automatizados, quando tratados sob os dois pontos de vista citados. O ambiente SGC é um sistema aberto, a fim de permitir o fácil acoplamento de novas facilidades, bem como mostra-se um sistema prático para suportar rotinas de teste e caracterização em laboratório.This work deals with software environments for automatic test and characterization of electro-electronical devices, components and circuits. Special attention is paid to the features of testing and characterizing integrated devices and circuits. The subject is treated in two different and complementary views: i) The needs of the test and characterization engineer are addressed. The test engineer carries out physical experiments, which embody measurements and data acquisitions, data processing, visualization and analysis. ii) The needs of the software tools developer, who develops computer programs for the automation of the procedures that are usually carried out during test and characterization, are also addressed. After the analysis of the subject under study, a software framework, called SGC ("Sistema de Gerenciamento e Controle"), is proposed and implemented. The SGC Framework was implemented under MS-WindowsTm using a object oriented approach. The SGC framework aims to fulfill the needs inherent to the automatic test and characterization, when treated using the approaches mentioned above. The SGC Framework is a open system, supporting the easy integration of new software functions to the environment, as well as a practical system for test and characterization laboratory routines

SGC : um ambiente para a automação de procedimentos de caracterização e teste

Este trabalho trata de ambientes de software para a realização de teste e caracterização de dispositivos, componentes ou circuitos eletro-eletrônicos, de forma automatizada. Ênfase especial é dada à problemática relacionada ao teste e caracterização automatizados de dispositivos e circuitos integrados. O assunto é tratado sob dois pontos de vista distintos e complementares: i) Sob o ponto de vista do engenheiro de teste e caracterização, que realiza experimentos físicos, que são as medidas e aquisições de dados, processa, visualiza e analisa dados. ii) Sob o ponto de vista do projetista de ferramentas de software, que desenvolve programas de computador para automatizar as tarefas rotineiramente realizadas durante o teste e a caracterização. Após a analise do assunto em questão, um ambiente de software (Framework), chamado SGC, é proposto e implementado. O SGC foi implementado em ambiente MS-WindowsTM através de um paradigma de orientação a objetos, e pretende atender as necessidades inerentes ao teste e caracterização automatizados, quando tratados sob os dois pontos de vista citados. O ambiente SGC é um sistema aberto, a fim de permitir o fácil acoplamento de novas facilidades, bem como mostra-se um sistema prático para suportar rotinas de teste e caracterização em laboratório.This work deals with software environments for automatic test and characterization of electro-electronical devices, components and circuits. Special attention is paid to the features of testing and characterizing integrated devices and circuits. The subject is treated in two different and complementary views: i) The needs of the test and characterization engineer are addressed. The test engineer carries out physical experiments, which embody measurements and data acquisitions, data processing, visualization and analysis. ii) The needs of the software tools developer, who develops computer programs for the automation of the procedures that are usually carried out during test and characterization, are also addressed. After the analysis of the subject under study, a software framework, called SGC ("Sistema de Gerenciamento e Controle"), is proposed and implemented. The SGC Framework was implemented under MS-WindowsTm using a object oriented approach. The SGC framework aims to fulfill the needs inherent to the automatic test and characterization, when treated using the approaches mentioned above. The SGC Framework is a open system, supporting the easy integration of new software functions to the environment, as well as a practical system for test and characterization laboratory routines

Medidas elétricas em microestruturas integradas sobre silício

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RTS noise in semiconductor devices : time constants estimates and observation window analysis

We obtained a semi-analytical treatment considering estimators for the variance and variance of variance for the RTS noise as a function of the time observation. Our method also suggests a way to experimentally determine the constants of capture and emission in the case of a dominant trap and uni- versal behaviors for the superposition from many traps. We present detailed closed-form expressions corroborated by MC simulations. We are sure to have an important tool to guide developers in building and analyzing low-frequency noise in semiconductor devices